Modern three dimensional memory arrays (such as vertical NAND flash memory devices) include a stack of at least one pair of isolating and conductive layers. Sequences of flash memory cells are connected to each other by vertical bitlines. A vertical bitline is manufactured by forming a high aspect ratio (HAR) hole in the isolating and conductive layers and then filling the HAR hole with a conductive material.
The HAR hole may exhibit a high aspect ratio (ratio between the width of the HAR hole and its depth) of 1:30-1:100.
The HAR hole has a nanometric scale cross section (diameter of nanometers) and its bottom cannot be properly imaged by an optical tools. In most cases electron beam imaging of the bottom of the HAR hole is not possible as the electrons that impinge on the bottom of the HAR hole do not manage to exit the HAR hole and be detected by an electron detector and thus the image of the HAR hole does not include sufficient information.
There is a growing need to evaluate HAR holes of nanometric scale.